Design Implementation Engineer
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Job description
Join VeroTech as a Design Implementation Engineer and become part of our community where innovation and people come first. You'll take on exciting technical challenges and develop your expertise while creating solutions that drive progress across several industries. About the role As a Physical ASIC Design Implementation Engineer, you will be at the forefront of technology, leveraging full backend expertise for P&R projects. You will engage directly with customers for future projects and possess a robust grasp of the Cadence Place & Route flow. You'll also take the reins on partitioning, split the top-level SDC file into timing budget and constraints, and lead discussions on specifications with customers., Lead the Physical Design implementation team through the full chip design cycle to ensure signoff closure for tape-out. Serve as the technical interface to customers to address their specifications. Set up and optimize the flow for specific library sets and foundry nodes. Develop low power designs (UPF) and debug SDC files. Design and implement Floorplanning & power grid for both toplevel and block levels. Execute Place, CTS & Routing while resolving setup & hold violations. Conduct sign-off extraction, timing analysis, power analysis, and physical verification.
Requirements
We require an experienced engineer with profound knowledge of the full ASIC back-end design flow and leadership capabilities. Ideal candidates will have: Expert knowledge of setup and sign-off extraction using SPEF/QUANTUS. Proficiency in timing (TEMPUS), Power analysis (VOLTUS), and Physical verification processes. Strong skills in Floorplanning, power grid design, and physical verification including DRC, ERC, LVS, and ANT. Prior experience with technical leadership of a project.